Semiconductor memory is a resource in modern computers used for data storage and program execution. Current trends in memory technology are toward greater density (more memory locations, or “cells,” per memory device), higher speed, and improved efficiency.
There are various types of semiconductor memory, including volatile memory and non-volatile memory. A commonly used type of volatile memory is known as static random access memory, or “SRAM”. SRAMs are widely used in applications where speed is of primary importance, such as the cache memory typically placed proximate to the processor or Central Processing Unit (CPU) in a personal computer or system on a chip.
A typical SRAM cell 50, comprised of six MOSFETS M51-M56, is now described with reference to FIG. 1. Multiple such SRAM cells 50 are used to form a SRAM array. Transistors M51-M52 form a first inverter 52, and transistors M53-M54 form a second inverter 54. The inverters 52 and 54 are cross-coupled. A bit of data is stored on the transistors M51-M54 forming the inverters 52 and 54. Transistors M55 and M56 act as pass gates controlling access to the SRAM cell 50 during read and write operations. Access to the SRAM cell 50 is enabled by the word line WL which controls the two pass gate transistors M55 and M56 which, in turn, control whether the SRAM cell 50 is connected to the bit lines BL and BLB. Bit lines BL and BLB are used to transfer data for both read and write operations. During read operations, the bit lines BL and BLB are actively driven high and low by the inverters 52 and 54, permitting readout by a sense amplifier (not shown). Prior to each access, the bit lines BL and BLB are pre-charged to a prescribed logic level.
The entire time interval required to complete a read or write operation to the SRAM cell 50 is termed the read cycle time or write cycle time. The read operation, and thus the read cycle time, has two components: a read access interval and a read pre-charge interval. During the read access interval, the logic state of the SRAM cell 50 is acquired by the associated sense amplifier. During the pre-charge interval, the bit lines BL and BLB are pre-charged to prepare for the next read operation. A read operation, and thus the read cycle time, can be considered to include a read access interval and then a read pre-charge interval, or a read pre-charge interval and then a read access interval.
A write operation, and thus the write cycle time, similarly includes a write access interval (during which the input data is transferred into the SRAM cell 50), and a write pre-charge interval. A write operation, and thus the write cycle time, can be considered to include a write access interval and then a write pre-charge interval, or a write pre-charge interval and then a write access interval.
For most SRAM cells 50, the read and write cycle times are not equal. The read access interval is typically longer than the write access interval, while the write pre-charge interval is generally longer than the read pre-charge interval.
The speed and efficiency of the SRAM cell 50 may be critically affected by these timings. For example, the read and write pre-charge intervals may be an appreciable portion of the read and write cycle times, and sense amplifier usage may contribute significantly to the overall power consumption of the SRAM cell 50. In early SRAM cell 50 designs, read and write cycle times were based on an externally generated clock signal. For example, if the SRAM cell 50 were used in a SRAM array used by a microcomputer, the bus clock in the memory interface would determine the read and write cycle times of the SRAM cells 50.
Though conceptually simple, reliance on the bus clock results in excessive power consumption. To overcome this inefficiency, manufacturers of SRAM arrays incorporated “self-time” circuitry into the SRAM arrays, to control timing independently of the externally generated clock signal. The self-time circuitry establishes the read and write access intervals, together with the subsequent read and write pre-charge intervals.
The self-time circuitry establishes the write cycle time by performing a dummy write operation on dummy SRAM cells of a dummy SRAM array. It is critical to ensure that the write cycle time is sufficient such that every SRAM cell in the SRAM array is writeable in the write cycle time determined by the self-time circuitry. Due to the very large number of SRAM cells 50 in a given SRAM array, a high sigma in statistical variation in operation of the transistors forming the SRAM cells 50 of the SRAM array must be accounted for.
A known dummy SRAM array 20 is shown in FIG. 2. Here, in addition to a first dummy SRAM cell 10 (a replica of that described above as SRAM cell 50), there is a second dummy SRAM cell 25 of the same configuration.
In the second dummy SRAM cell 25, transistors M7-M8 form a first inverter 16, and transistors M9-M10 form a second inverter 18. The inverters 16 and 18 are cross-coupled. Transistors M11 and M12 act as pass gates controlling access to the dummy SRAM cell 25 during its write operation, which proceed as described above. In addition, here it can be observed that transistors M15, M16 drive the dummy word line DWL.
This dummy SRAM array 20 performs a dummy write operation to determine the write cycle time for the SRAM array. The dummy write operation tracks the write cycle time of the SRAM cells 50 of the SRAM array to ensure that even the slowest SRAM cell is writeable in the determined write cycle time.
Three techniques to accomplish this tracking are used together in the dummy SRAM array 20. One is to simply increase the length of the dummy word line DWL path, which introduces additional resistance and capacitance into the dummy word line DWL path, represented by the resistor R, and the capacitors C1, C2. The values of the resistor R and the capacitors C1, C2 can be chosen through pie modeling of the resistance and capacitance of different devices and metals. The next technique is to vary the write driver 21 (formed from transistors M13, M14) size to vary how quickly the dummy bit lines DBL and DBLB fall, and/or to use inverters (e.g., INV1, INV2) to introduce delay to actuation of the write driver 21. The remaining technique is to vary the size of the capacitor C3 on the dummy complementary bitline DBLB. When the dummy write cycle is complete, the dummy SRAM array 20 asserts the reset signal output by inverter INV3. The reset signal is used in generating an internal clock utilized by both the dummy SRAM cells 10, 25 as well as the SRAM cells 50, which in turn is used to set read and write cycle times.
These techniques, either alone or in conjunction with each other, serve to introduce delay into the write cycle time to ensure that even the slowest SRAM cell 50 of the SRAM array is writeable in the write cycle time.
While the dummy SRAM array 20 accomplishes its goal, it results in a performance penalty to SRAM array 20. This penalty results from the fact that the dummy SRAM array 20 introduces delay suitable for the worst possible variation in PVT (process, voltage, temperature). Thus, the delay introduced may actually be in excess of what is actually required under current PVT conditions. Therefore, there is a need for better tracking of the PVT of the SRAM array 20 such that a more optimal read cycle time or write cycle time can be determined.